Translation Look-aside Buffer - definizione. Che cos'è Translation Look-aside Buffer
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Cosa (chi) è Translation Look-aside Buffer - definizione

MEMORY CACHE THAT IS USED TO REDUCE THE TIME TAKEN TO ACCESS A USER MEMORY LOCATION; PART OF THE CHIP’S MEMORY-MANAGEMENT UNIT
Translation-Lookaside Buffer; Translation-lookaside buffer; Translation Lookaside Buffer; Address Translation Registers; ITLB; DTLB; TLB flush; Process context identifiers; Process-context identifier; Process context identifier; Address space number; Translation look-aside buffer; Speculative translation lookaside buffer; Secondary translation lookaside buffer
  • location=United States of America}}</ref> shows the working of a translation lookaside buffer. For simplicity, the page-fault routine is not mentioned.
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Translation Look-aside Buffer         
<storage, architecture> (TLB) A table used in a {virtual memory} system, that lists the physical address page number associated with each virtual address page number. A TLB is used in conjunction with a cache whose tags are based on virtual addresses. The virtual address is presented simultaneously to the TLB and to the cache so that cache access and the virtual-to-physical address translation can proceed in parallel (the translation is done "on the side"). If the requested address is not cached then the physical address is used to locate the data in main memory. The alternative would be to place the translation table between the cache and main memory so that it will only be activated once there was a cache miss. (1995-01-30)
Translation lookaside buffer         
A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location.
ITLB         
Instruction Translation Look-aside Buffer (Reference: CPU)

Wikipedia

Translation lookaside buffer

A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location. It can be called an address-translation cache. It is a part of the chip's memory-management unit (MMU). A TLB may reside between the CPU and the CPU cache, between CPU cache and the main memory or between the different levels of the multi-level cache. The majority of desktop, laptop, and server processors include one or more TLBs in the memory-management hardware, and it is nearly always present in any processor that utilizes paged or segmented virtual memory.

The TLB is sometimes implemented as content-addressable memory (CAM). The CAM search key is the virtual address, and the search result is a physical address. If the requested address is present in the TLB, the CAM search yields a match quickly and the retrieved physical address can be used to access memory. This is called a TLB hit. If the requested address is not in the TLB, it is a miss, and the translation proceeds by looking up the page table in a process called a page walk. The page walk is time-consuming when compared to the processor speed, as it involves reading the contents of multiple memory locations and using them to compute the physical address. After the physical address is determined by the page walk, the virtual address to physical address mapping is entered into the TLB. The PowerPC 604, for example, has a two-way set-associative TLB for data loads and stores. Some processors have different instruction and data address TLBs.